1. Field of Invention
This invention relates to a semiconductor package and a manufacturing method thereof. More particularly, the present invention is related to a semiconductor package module and a manufacturing method thereof.
2. Related Art
Integrated circuit (chip) packaging technology is becoming a limiting factor for the development in packaged integrated circuits of higher performance. Semiconductor package designers are struggling to keep pace with the increase in pin count, size limitations, low profile, and other evolving requirements for packaging and mounting integrated circuits.
Originally, a semiconductor package is formed by the steps of singulating a wafer into a plurality of chips, disposing one of the chips on a substrate, electrically connecting the chip and the substrate by conductive wires and encapsulating the chips via an encapsulation.
As shown in FIG. 1, there is provided a stacked semiconductor package. Therein, the projective area of the upper chip is larger than that of the lower chip, so the lower chip 12 can be electrically connected to the substrate 13 via the conductive wires 15. On the contrary, when the projective area of the upper chip is equal to the projective area of the lower chip, the lower chip will not be able to be connected to the substrate for that there is not enough space for wire-bonding. Accordingly, there is a restriction in such stacked package. Moreover, the conductive wire 14 is so long. Accordingly, said conductive wire 14 and said conductive wire 15 will be easily to be bonded to each other due to the molding compound sweeping the conductive wires 14 and 15. Besides, the length of the conductive wire 14 is large so as to cause the signal delay and decay, and reduce the electrical performance of said stacked package.
Next, there is provided another conventional stacked semiconductor package in FIG. 2. As FIG. 2 shown, a first chip 21 is disposed on a first substrate 22 and electrically connected to the first substrate 22 so as to form a first package. Therein, the first chip 21 can be mounted to the first substrate 22 via bumps in a flip-chip manner. In addition, the first chip 21 also can be mounted to the first substrate 22 and electrically connected to the first substrate 22 via conductive wires by the method of wire-bonding. Similarly, a second chip 23 can be electrically connected to a second substrate 24 by flip-chip bonding or wire-bonding, and a third chip 25 can also be electrically connected to a third substrate 26 by flip-chip bonding or wire-bonding. As mentioned above, in order to have the first package, the second package, the third package electrically connected to each other, there shall be provided an inter-substrate 27 as an electrical interconnection between said packages. In such a manner, a package module can be provided. For example, a plurality of memory chips can be electrically connected with each other to expand the memory capacity according to said package module. However, said package module comprises at least an inter-substrate regarded as an electrical interconnection between said packages, so the overall thickness of the package module will be increased.
Therefore, providing another semiconductor package and package module to solve the mentioned-above disadvantages is the most important task in this invention.